/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "../core/defines.v"
`timescale 1ns/1ps

module tagv_cache(
	input	wire			clk,
	input	wire			rst_n,

	input	wire			en_i,
	input	wire[4:0]		addr_i,
	input	wire			we_i,
	input	wire[29:0]		wdata_i,

	output	wire[29:0]		rdata_o
	);

	//	{valid-1, dirty-1, tag-29}
	reg[29:0]	tagv[31:0];
	reg[4:0]	addr;
	integer		loop;

	initial begin
		for (loop = 0; loop < 30; loop = loop + 1) begin
			tagv[loop] = 30'h0;
		end
	end

	always @(posedge clk) begin
		if (rst_n == `RESET_ENABLE) begin
			addr <= 5'h0;
		end else begin
			if (en_i) begin
				if (we_i) begin
					tagv[addr_i] <= wdata_i;
				end

				addr <= addr_i;
			end
		end
	end

	assign rdata_o = (rst_n == `RESET_ENABLE) ? 30'h0 : tagv[addr];

endmodule
